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april 2012 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression fab2210 ? audio subsyste m with class-g headphone and 3.3w mono class-d speaker with dynamic range compression features ? high-efficiency stereo class-g headphone - 100db snr headphone amplifier - capacitor-free outputs for high-frequency response ? mono filterless class-d speaker amplifier - 91% efficiency for extended battery runtime - drc for louder spl and speaker protection - 3.3w into 4 ? at 5.0v, thd+n < 10% - 1.27w into 8 ? at 4.2v, thd+n < 10% - low emi edge-rate controlled output - 97db signal-to-noise ratio (snr) ? click and pop suppression ? selectable single-ended or differential audio inputs for high common-mode rejection ? high power supply rejection ration (psrr) rejects 217hz gsm noise ? highly configurable using i 2 c control ? low-power, software standby mode description the fab2210 combines a class-g stereo capacitor- free headphone amplifier with a mono class-d speaker amplifier into one ic package. the headphone and speaker amplifiers incorporate class-g and class-d topologies, respectively, for low power dissipation, which extends battery runtime. the class-g headphone amplifier incorporates an integrated charge pump t hat generates a negative supply rail for ground-centered headphone outputs. the class-d amplifier includes programmable dynamic range compression (drc) that maximizes sound pressure level (spl) for maximum loudness, while protecting the speaker from damage. the noise gate can automatical ly mute the speaker or headphone amplifiers to reduce noise when input signals are low. ordering information part number operating temperature range package packing method FAB2210UCX -40c to +85c 20-bump, wafer-level chip-scale package (wlcsp), 0.4mm pitch 3000 units on tape & reel typical application circuit class-g cap-free headphone amps 0db / 1.5db / 3db / 6db 16db/20db/24db class-d speaker amp charge pump sout+ sout- houtr houtl hsense mixer/ mux ina1 ina2 inb1 inb2 i2c scl sda hvdd cp+ cp- hvss dvdd preamp a -3db to 18db preamp b -3db to 18db sgnd 2.8v ? 5.25v svdd noise gate dgnd speaker volume 2.2f 2.2f 2.2f 2.2f 0.1f 0.1f 0.1f 0.1f 2.2f 10f 1.6v ? 2.8v headphone volume -64db to 0db -64db to 0db noise gate / drc figure 1. typical application circuit
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 2 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression pin configuration figure 2. pin assignments, top view (bump side down) pin definitions pin # name type description a2 svdd power input power supply for class-d amplifier c1 sgnd power input class-d amplifier ground c2 dvdd power input power supply for charge pump a3 dgnd power input headphone amplifier ground c3 hvdd power output charge pump output; positive power supply for headphone amplifier, input preamplifiers, and mixers c4 hvss power output charge pump output; negative mirror of hvdd b4 cp+ power charge pump flying capacitor positive terminal a4 cp- power charge pump flying capacitor negative terminal e3 nc no connect no connect can be tied to sgnd for additional thermal dissipation d1 ina1 input single-ended line level audio input a1 (or non-inverting differential input ina+) e1 ina2 input single-ended line level audio i nput a2 (or inverting differential input ina-) d2 inb1 input single-ended line level audio input b1 (or non-inverting differential input inb+) e2 inb2 input single-ended line level audio i nput b2 (or inverting differential input inb-) e4 houtl output left headphone amplifier output d4 houtr output right he adphone amplifier output d3 hsense input sense ground; connect to dg nd close to shield terminal of headphone jack a1 sout+ output positive class-d amplifier output b1 sout- output negative class-d amplifier output b3 scl input i 2 c clock input b2 sda bidirectional i 2 c data i/o
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 3 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. all voltages are referenced to gnd. symbol parameter min. max. unit v dd voltage on svdd pin -0.3 6.0 v v dvdd voltage on dvdd pin -0.3 3.2 v v svdd voltage on svdd + dvdd pins 8 v v in voltage on ina1, ina2 , inb1, inb2 pins v hvss -0.3 v dvdd +0.3 or 2.1 (1) v v hout voltage on houtl, houtr pins v hvss -0.3 v dvdd +0.3 v v sense voltage on hsense pin -0.3 0.3 v v d voltage on sda, scl pins -0.3 v svdd v v sout voltage on sout+, sout- pins -0.3 v svdd +0.3 v r hp headphone impedance 12.8 ? note: 1. whichever is less. reliability information symbol parameter min. typ. max. unit t j junction temperature 150 c t stg storage temperature range -65 150 c t l lead temperature (soldering, 10 seconds) 300 c ja thermal resistance, jedec standard, multilayer test boards, still air 66 c/w tsd thermal shutdown threshold 150 c t hys thermal shutdown hysteresis 15 c electrostatic discharge protection symbol parameter min. unit esd human body model; jesd22-a114 level 2; compatible with iec61340-3-1: 2002 level 2 or esd-stm5.1-2001 level 2 or mil-std-883e 3015.7 level 2 2.00 kv charged device model; jesd22-c101 level iii compatible with iec61340-3-3 level c4 or esd-stm5.3.1-1999 level c4 1.25 kv recommended operating conditions the recommended operating conditions table defines th e conditions for actual device operation. recommended operating conditions are specified to en sure optimal performance to the datash eet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit t a operating temperature range -40 85 c v svdd speaker supply voltage range (2,3) 2.80 3.60 5.25 v v dvdd headphone supply voltage range (2,3) 1.6 1.8 2.8 v notes: 2. v svdd must be greater than or equal to v dvdd at all times. 3. v svdd and v dvdd slew rates must be less than 1v/s.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 4 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression electrical characteristics unless otherwise noted: audio bw=22hz to 20khz, f in =1khz, difa=1, difb=0, hp_amix=0, hp_bmix=1, sp_amix=1, sp_bmix=0, unused inputs are ac grounde d, drc is off, preamplifie r gains=0db, headphone volume=0db, headphone amplifier gain=0db, speaker volume =0db, sp_gain=00, edge-rate control is on, spread spectrum is on, hp_ng_rat=100, sp_ng_rat= 001, srst=0, sda and scl pull-up voltage=dv dd , z spk =8 ? +33h, r hp =32 ? , hp_hiz=0, sv dd =3.6v, dv dd =1.8v, and t a =25c. symbol parameter condition min. typ. max. unit i stby standby current (srst=1) svdd + dvdd 2 a t on turn-on time time from standby to full speaker and headphone operation, zcd and ramps disabled 1.6 ms r in input resistance preamplifier gain=12.0db 7.7 k ? preamplifier gain=6.0db 12.8 preamplifier gain=4.5db 14.3 preamplifier gain=3.0db 15.9 preamplifier gain=1.5db 17.5 preamplifier gain=0.0db 19.2 preamplifier gain=-1.5db 20.8 preamplifier gain=-3.0db 22.4 maximum input signal swing (sv dd =2.8v to 5.25v, single- ended input) preamplifier gain=0db v dvdd v pk-pk preamplifier gain=12db v dvdd 4 v pk-pk
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 5 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression electrical characteristi cs (speaker amplifier) unless otherwise noted: audio bw=22hz to 20khz, f in =1khz, difa=1, difb=0, hp_amix=0, hp_bmix=0, sp_amix=1, sp_bmix=0, unused inputs are ac gr ounded, drc is off, preamp lifier gains=0db, headphone volume=0db, headphone amplifier gain=0db, speaker volu me=0db, sp_gain=00, edge-rate control is on, spread spectrum is on, hp_ng_rat=000, sp_ng_rat= 000, srst=0, sda and scl pull-up voltage=dv dd , z spk =8 ? +33h, r hp =32 ? , hp_hiz=0, sv dd =3.6v, dv dd =1.8v, and t a =25c. symbol parameter condition min. typ. max. unit i cc current consumption sp_ng_rat=001 sv dd 2.7 ma dv dd 1.6 v os output offset voltage vo lume=0db 0.4 mv psrr power-supply rejection ratio 200mv pk-pk ripple on sv dd , sp_ng_rat=001 f=217hz 70 db f=1khz 70 f=20khz 63 200mv pk-pk ripple on sv dd f=217hz 74 f=1khz 70 f=20khz 44 p out output power thd+n < 10%, sv dd =5.0v, z spk =4 ? + 33h 3.3 w thd+n < 1%, sv dd =5.0v, z spk =4 ? + 33h 2.6 thd+n < 10%, sv dd =4.2v 1.27 thd+n < 1%, sv dd =4.2v 1.00 thd+n < 10%, sv dd =3.6v 0.92 thd+n < 1%, sv dd =3.6v 0.73 thd+n total harmonic distortion plus noise p out =0.7w, sv dd =4.2v 0.04 % p out =0.7w, sv dd =3.6v 0.17 snr signal-to-noise ratio a-wt, p out =700mw 97 db a-wt, p out =700mw, sv dd =4.2v 97 class-d frequency spread spectrum 300 khz fixed frequency 300 efficiency p out =720mw 91 % dc detect voltage absolute value, measured differentially across sout+ and sout- 1.5 v pk t dcerr dc detect time dcerr_time=10 15 ms dcerr_time=01 5 dcerr_time=00 2 single-ended output impedance amp. off, sp_hiz=0, f < 40khz 2 k ? otp_err=1, f < 40khz 2 dc_err=1, f < 40khz 2 amp. off, sp_hiz=1, f < 40khz 35 ocp_err=1, f < 40khz 2
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 6 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression electrical characteristi cs (headphone amplifiers) unless otherwise noted: audio bw=22hz to 20khz, f in =1khz, difa=1, difb=0, hp_amix=0, hp_bmix=1, sp_amix=0, sp_bmix=0, unused inputs are ac grounde d, drc is off, preamplifie r gains=0db, headphone volume=0db, headphone amplifier gain=0db, speaker volume =0db, sp_gain=00, edge-rate control is on, spread spectrum is on, hp_ng_rat=000, sp_ng_rat= 000, srst=0, sda and scl pull-up voltage=dv dd , z spk =8 ? +33h, r hp =32 ? , hp_hiz=0, sv dd =3.6v, dv dd =1.8v, and t a =25c. symbol parameter condition min. typ. max. unit i cc current consumption hp_ng_rat=100 svdd 0.8 ma dvdd 1.9 v os output offset voltage volume=mute 0.1 mv psrr power-supply rejection ratio 200mv pk-pk ripple on svdd, hp_ng_rat=100 f=217hz 93 db f=1khz 94 f=20khz 97 200mv pk-pk ripple on svdd f=217hz 93 db f=1khz 93 f=20khz 97 p out output power thd+n < 0.1% 27 mw thd+n < 1%, headphone amplifier gain=6db 29 thd+n < 1%, headphone amplifier gain=6db, sv dd =4.2v 29 thd+n total harmonic distortion plus noise p out =10mw 0.01 % p out =10mw, sv dd =4.2v 0.01 p out =20mw 0.01 snr signal-to-noise ratio a-wt, hp_ng_rat =100 p out =10mw, sv dd =3.6v 102.5 db p out =10mw, sv dd =4.2v 102.5 p out =20mw 105.5 a-wt, hp_ng_rat =000 p out =10mw, sv dd =3.6v 97 p out =10mw, sv dd =4.2v 97 p out =20mw 100 c l capacitive drive 100 pf xtak crosstalk p out =10mw, f=100hz -96 db p out =20mw, f=100hz -95 p out =10mw, f=1khz -93 p out =20mw, f=1khz -92 p out =10mw, f=10khz -79 p out =20mw, f=10khz -79 headphone to speaker, p out =10mwx2 -91 speaker to headphone, p out =700mw -106 output impedance amp. off, hp_hiz=0 130 ? otp_err=1 170 ? amp. off, hp_hiz=1 15 k ?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 7 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression i 2 c dc electrical characteristics unless otherwise noted, sv dd =2.8v to 5.25v, dv dd =1.6v to 2.8v, t a =-40c to 85c. symbol parameter fast mode (400khz) min. max. unit v il low-level input voltage -0.3 0.6 v v ih high-level input voltage 1.3 v v ol low-level output voltage at 3ma sink current (open-drain or open-collector) 0 0.4 v i ih high-level input current of ea ch i/o pin, input voltage=v svdd -1 1 a i il low-level input current of each i/o pin, input voltage=0v -1 1 a i 2 c ac electrical characteristics unless otherwise noted, sv dd =2.8v to 5.25v, dv dd =1.6v to 2.8v, t a =-40c to 85c. symbol parameter fast mode (400khz) min. max. unit f scl scl clock frequency 0 400 khz t hd;sta hold time (repeated) start condition 0.6 s t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t su;sta set-up time for repeated start condition 0.6 s t hd;dat data hold time 0 0.9 s t su;dat data set-up time (4) 100 ns t r rise time of sda and scl signals (5) 20+0.1c b 300 ns t f fall time of sda and scl signals (5) 20+0.1c b 300 ns t su;sto set-up time for stop condition 0.6 s t buf bus-free time between stop and start conditions 1.3 s t sp pulse width of spikes that must be suppressed by the input filter 0 50 ns notes: 4. a fast-mode i 2 c-bus? device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat ? 250ns must then be met. this is automatically the case if the device does not stre tch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the serial data (sda) line t r_max + t su;dat= 1000 + 250=1250ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 5. c b equals the total capacitance of one bus line in pf. if mixe d with high-speed mode devices, faster fall times are allowed according to the i 2 c specification. figure 3. definition of timing for full-speed mode devices on the i 2 c bus
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 8 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression typical performance characteristics system unless otherwise noted: audio bw=22hz to 20khz, f in =1khz, difa=1, difb=0, hp_amix=0, hp_bmix=1, sp_amix=1, sp_bmix=0, unused inputs are ac gr ounded, drc is off, preamp lifier gains=0db, headphone volume=0db, headphone amplifier gain=0db, speaker volu me=0db, sp_gain=00, edge-rate control is on, spread spectrum is on, hp_ng_rat=100, sp_ng_rat= 001, srst=0, sda and scl pull-up voltage=dv dd , z spk =8 ? +33h, r hp =32 ? , hp_hiz=0, sv dd =3.6v, dv dd =1.8v, and t a =25c. figure 4. quiescent current vs. supply voltage figure 5. quiescent current vs. supply voltage figure 6. quiescent current vs. supply voltage figure 7. quiescent current vs. supply voltage figure 8. standby current vs. supply voltage figure 9. input resistance vs. preamplifier gain 2 2.5 3 3.5 4 2.533.544.555.5 svdd current (ma) svdd voltage (v) speaker amplifier mode inputs ac grounded hp_bmix = 0 hp_ng_rat[2:0] = 000 sp_ng_rat[2:0] = 001 0 0.5 1 1.5 2 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 dvdd current (ma) dvdd voltage (v) speaker amplifier mode inputs ac grounded hp_bmix = 0 hp_ng_rat[2:0] = 000 sp_ng_rat[2:0] = 001 0 0.5 1 1.5 2 2.533.544.555.5 svdd current (ma) svdd voltage (v) headphone amplifier mode inputs ac grounded sp_amix = 0 hp_ng_rat[2:0] = 100 sp_ng_rat[2:0] = 000 0 0.5 1 1.5 2 2.5 3 3.5 1.6 1.8 2 2.2 2.4 2.6 2.8 dvdd current (ma) dvdd voltage (v) headphone amplifier mode inputs ac grounded sp_amix = 0 hp_ng_rat[2:0] = 100 sp_ng_rat[2:0] = 000 1 2 3 4 5 6 7 8 9 10 2.5 3 3.5 4 4.5 5 5.5 svdd current (a) svdd voltage (v) srst = 1 -4 -2 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 preamplifier gain (db) input resistance (kohm)
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 9 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression typical performance characteristics speaker amplifier unless otherwise noted: audio bw=22hz to 20khz, f in =1khz, difa=1, difb=0, hp_amix=0, hp_bmix=0, sp_amix=1, sp_bmix=0, unused inputs are ac gr ounded, drc is off, preamp lifier gains=0db, headphone volume=0db, headphone amplifier gain=0db, speaker volu me=0db, sp_gain=00, edge-rate control is on, spread spectrum is on, hp_ng_rat=000, sp_ng_rat= 000, srst=0, sda and scl pull-up voltage=dv dd , z spk =8 ? +33h, r hp =32 ? , hp_hiz=0, sv dd =3.6v, dv dd =1.8v, and t a =25c. figure 10. thd+n vs. output power figure 11. thd+n vs. frequency figure 12. output power vs. supply voltage figure 13. efficiency vs. output power figure 14. psrr vs. frequency figure 15. frequency response 0.01 0.1 1 10 0.001 0.01 0.1 1 10 thd+n (%) output power (w) svdd=2.8v svdd=3.6v svdd=4.2v svdd=5.0v f = 1khz z spk = 8ohm+33uh 0.01 0.1 1 10 0.01 0.1 1 10 100 thd+n (%) frequency (khz) p out = 500mw z spk = 8ohm+33uh 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.533.544.555.5 output power (w) svdd voltage (v) thd+n = 10% thd+n = 1% f = 1khz z spk = 8ohm+33uh 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 efficiency (%) output power (w) svdd = 3.6v svdd = 4.2v f = 1khz z spk = 8ohm+33uh 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 100 psrr (db) frequency (khz) inputs ac grounded v ripple = 200mv pp sp_ng_rat = 000 -15 -10 -5 0 5 10 0.01 0.1 1 10 100 amplitude (db) frequency (khz) cin = 1.0uf cin = 0.1uf bw = <10hz to 80khz p out = 700mw
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 10 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression typical performance characteristics speaker amplifier (continued) figure 16. output vs. frequency headphone amplifiers unless otherwise noted: audio bw=22hz to 20khz, f in =1khz, difa=1, difb=0, hp_amix=0, hp_bmix=1, sp_amix=0, sp_bmix=0, unused inputs are ac grounde d, drc is off, preamplifie r gains=0db, headphone volume=0db, headphone amplifier gain=0db, speaker volume =0db, sp_gain=00, edge-rate control is on, spread spectrum is on, hp_ng_rat=000, sp_ng_rat= 000, srst=0, sda and scl pull-up voltage=dv dd , z spk =8 ? +33h, r hp =32 ? , hp_hiz=0, sv dd =3.6v, dv dd =1.8v, and t a =25c. figure 17. thd+n vs. output power figure 18. thd+n vs. frequency figure 19. power dissipation vs. output power figure 20. crosstalk vs. frequency -150 -120 -90 -60 -30 0 0 5 10 15 20 amplitude (dbv) frequency (khz) f= 1khz 0.01 0.1 1 10 0.01 0.1 1 10 100 thd+n (%) output power (mw) f = 1khz hp_gain[1:0] = 11 0.001 0.01 0.1 1 0.01 0.1 1 10 100 thd+n (%) frequency (khz) pout = 10mw/channel pout = 20mw/channel c in = 1uf hp_gain[1:0] = 11 0 10 20 30 40 50 60 70 0 1020304050607080 power dissipation (mw) output power(mw) f = 1khz hp_gain[1:0] = 11 hp_ng_rat[2:0] = 000 -120 -100 -80 -60 -40 -20 0 0.01 0.1 1 10 100 crosstalk (db) frequency (khz) p out = 10mw
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 11 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression typical performance characteristics headphone amplifiers (continued) figure 21. psrr vs. frequency figure 22. frequency response figure 23. output vs. frequency 0 20 40 60 80 100 120 0.01 0.1 1 10 100 psrr (db) frequency (khz) inputs ac grounded v ripple = 200mv pp hp_ng_rat = 000 -15 -10 -5 0 5 10 0.01 0.1 1 10 100 amplitude (db) frequency (khz) cin = 1.0uf cin = 0.1uf bw = <10hz to 80khz p out = 10mw -160 -140 -120 -100 -80 -60 -40 -20 0 0 5 10 15 20 amplitude (dbv) frequency (khz) f= 1khz hp_ng_rat = 000
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 12 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression detailed description shutdown modes standby when the srst bit is set to 1, the fab2210 enters a low-power standby mode. while srst=1, i 2 c communications are available and i 2 c values are reset to default values. any values written to the i 2 c registers (except srst) while in standby mode are ignored and default values is preserved. to achieve low supply current during standby mode, all inputs must be dc. audio inputs must be ac grounded. v svdd and v dvdd must be within recommended operating conditions. i 2 c pins must be grounded or pulled high with no toggling. if ac is presented to the inputs during standby mode, standby current may increase slightly, but there are no other negative effects. thermal shutdown protection (tsp) if the junction temperature of the device exceeds the thermal shutdown threshold of 150c (see the electrical characteristics table) , the device protects itself by turning off the amplifiers. the i 2 c port remains functional and the otp_err bit is set to 1. other bits retain their values and are not reset. see the electrical characteristics table for output impedances. the amplifiers remain off until the junction temperature falls below the thermal shutdown recovery point and srst is cycled or power is cycled. over-current protection (ocp) if the speaker amplifier?s ou tput current limit of 1.3a peak is exceeded (see the electrical characteristics table) , the amplifier turns off. during current-limit shutdown, the i 2 c port remains functional and the ocp_err bit is set to 1. other bits retain their values and are not reset. the speaker amplifier remains off and the ocp_err remains high until srst is cycled or power is cycled. dc output protection if the magnitude of the speake r amplifier output voltage across sout+ and sout- exceeds the dc detect voltage of 1.5v pk for more than t dcerr (see the electrical characteristics table) , the speaker amplifier turns off. this protects the loudspeaker from damage due to dc signals. low-frequency audio input signals may trigger unintentional dc output shut down. set the input dc coupling capacitor value small enough to avoid a dc output shutdown caused by a low-frequency audio signal. for the default t dcerr setting of 2ms, the input dc-coupling capacitor value must be 0.1 ? f or lower. during dc output shutdown, the i 2 c port remains functional and the dc_err bit is set to 1. other bits retain their values and are not reset. the speaker amplifier remains off and the dc_err bit remains high until srst is cycled or power is cycled. signal path audio signals pass from the input pins through a preamplifier, a mixer, a vo lume control, and finally through an amplifier. the preamplifiers can be set to -3db to 18db of gain. the headphone and speaker paths have volume controls that range from -64db to 0db. the headphone amplifier has gain settings of 0db, 1.5db, 3db, and 6db. the speaker amplifier has gain settings of 16db, 20db, and 24db. a variety of combinations of the input signals can be routed from the preamplifie rs to the headphone and speaker volume blocks. routing is controlled by the hp_amix, hp_bmix, sp_amix, sp_bmix, difa, difb, and mono bits. for example, to connect the left headphone amplifier channel to ina1 and the right headphone amplifier channel to ina2, set hp_ami x to 1. hp_bmix, difa, and mono should be set to 0. to configure inb1 and inb2 as a differential input and route the signal to the speak er amplifier, set difb and sp_bmix to 1. sp_amix should be set to 0. when hp_amix and hp_bmix are both 0, the headphone amplifier is off. when sp_amix and sp_bmix are both 0, the speaker amplifier is off. unused audio input pins must be grounded either directly or through a dc-blocking capacitor. to prevent internal clipping in the headphone amplifier path, internal signal amplit udes from the preamplifier outputs to the headphone amp lifier input should not exceed a peak-to-peak voltage equivalent to v dvdd - 0.2v. if hp_mono = 1, the peak-to-peak voltage can be as high as (v dvdd * 2) - 0.2v. extra caution should be taken if mixing signals together. to prevent internal clippi ng in the speaker amplifier path, internal signal amplit udes from the preamplifier outputs to the speaker amplif ier input should not exceed a peak-to-peak voltage equivalent to v dvdd - 0.2v. extra caution should be taken if mixing signals together.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 13 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression charge pump the fab2210 includes an inverting charge pump that generates hvdd and hvss (the headphone amplifier power supplies) from the dvdd power supply input. the hvss rail is a negative mirror of hvdd and allows the headphone amplifier to be ground referenced. the ground-referenced biasing scheme allows the headphone amplifier outputs to be biased at ground while operating from a single external supply. this eliminates the need for the large, expensive, dc- coupling capacitors between the headphone amplifier output and load that are requ ired on traditional, single- supply, v dd /2, biased headphone amplifiers. the negative hvss rail allows the input preamplifiers to be ground referenced. input dc-blocking capacitors are still required at ina1, ina2, inb1, and inb2 if the audio source driving the input preamplifiers is biased above ground. the input dc-blocking capacitors are not required if the audio source driving the input preamplifiers is also ground referenced and does not present any dc offset to the fab2210. class-g operation compared with a traditional class-ab amplifier, the fab2210?s class-g architecture reduces power consumption and extends battery life during headphone playback. the power supply rails (hvdd and hvss) of the class-g headphone amplifier adapt to the level of audio signal present at the output. the adaptive nature of the power supply rails ensures that energy is not wasted during quiet passages of music or when the volume of the headphone path is reduced. during stereo headphone playback, when the headphone output amplitude is below the v th threshold level of 250mv pk (typical); the charge pump efficiently divides v dvdd so that v hvss = -v dvdd /2 and v hvdd = v dvdd /2. when the headphone output amplitude exceeds 250mv pk (typical), the charge pump generates higher magnitude rails, where v hvss =-v dvdd and v hvdd = v dvdd to allow for higher output amplitudes. due to the high crest factor of music and speech, a significant portion of the audio content is below the v th threshold, even at typical volume level settings for headphone playback. when operating at the lower magnitude rails, less power is dissipated within the headphone amplifier. the transition from the lower magnitude rails to the higher magnitude rails occurs fast enough to prevent audible artifacts during headphone playback. the transition from the higher m agnitude rails to the lower magnitude rails occurs 15ms (typical) from the last threshold crossing (low to high) and only after the headphone output amplitud e has stayed below the threshold level. the 15ms (typical) hysteresis prevents the headphone amplifier power rails from bouncing between high and low rails when the audio signal approaches the threshold level. due to the flexible input to output routing capabilities of the fab2210, additional logic added to the class-g audio-level-detection circuit ensures that enough headroom is available to avoid saturating the audio input signals at the ina1 , ina2, inb1, and inb2 preamplifiers. this is especially useful in cases where both the class-d amplifie r path and/or mono headphone path are selected for playback. figure 24. class-g headphone amplif ier power supply rail operation
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 14 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression headphone amplifier high-impedance mode the fab2210 headphone outputs are placed in a high- impedance mode by setting the hp_hiz bit to 1 and turning off the headphone amplifier. this can be useful if the system?s headphone jack is shared with other devices. for proper high-impedance operation, srst must be set to 0 and the headphone amplifier must be off (see hp_mono, hpamix, and hp_bmix register definitions) . voltages on the houtl and houtr pins must not exceed dvdd and must not be below -dvdd. headphone volume ramp and zero crossing detection the hp_svoff and hp_zcsoff bits control the headphone volume when hp_att is changed. hp_svoff and hp_zcsoff do not slow down turn-on or turn-off when using the hp_amix, hp_bmix, or srst bits. thermal shutdown conditions are not slowed by hp_svoff or hp_zcsoff. table 1. headphone volume - change behavior hp_svoff hp_zcsoff behavior when hp_att is changed 1 1 volume changes immediately. 1 0 for each channel, wait until a zero crossi ng occurs in the input before changing volume. if a zero crossing does not occur within 200s, volume is forced to the new setting. 0 1 volume is ramped to the new se tting at a rate of 200s per step. 0 0 volume is changed by one step when a zero crossing occurs. if a zero crossing does not occur within 200s, a step is forced. on ly the first zero crossing within 200s triggers a volume change; volume does not change again until the next 200s. headphone amplifier noise gate the headphone noise gate automatically reduces the headphone volume when its input amplitudes are low to reduce noise during inactivity. (this function is more useful for speech than music.) the amplitude is measured after input preamplifiers, but before the headphone volume control. the headphone noise gate?s threshold level is set by the hp_ng_rat register. the amplitudes of both channels must be less than the noise gate threshold for the hold-time determined by the ng_atrt register. the amount of volume reduction is set by the hp_ng_att register. the speed at which the volume is reduced is determined by the attack time setting in the ng_atrt register. when the volume is reduced by the noise gate, the hp_att register?s readback value remains unchanged. an internal register keeps track of the actual volume setting. if either headphone channel?s amplitude goes above the headphone noise gate threshold, headphone volume is raised back to the hp_att value at a rate determined by the release time setting in the ng_atrt register. if hp_mono=1, only left channel amplitude is monitored. to avoid unpredictable behavior, noise gate settings should not change while the headphone amplifier is on. class-d speaker amplifier the fab2210 utilizes a ?filt erless? modulation scheme to achieve 92% efficiency, extending battery life and reducing component count. the pulse-width modulated, differential outputs of the cla ss-d amplifier switch at 300khz. when an audio input signal is not present, the class-d outputs switch in-phase at 50% duty cycle, minimizing idle current and saving power. programmable spread spectrum modulation spread spectrum modulation is employed to reduce emi generated at the class-d am plifier outputs. spread spectrum modulates the class-d amplifier?s switching frequency by a programmabl e percentage centered around the base switching frequency of 300khz, dispersing the spectral energy of the switching waveform over a wider band. this significantly reduces the amount of concentrated s pectral energy at multiples of the switching frequency th at fixed-frequency class-d amplifiers emit. spread spec trum modulation eliminates the need for output filters, as long as the distance from the class-d amplifier outputs to the speaker transducer is kept short. edge rate control (erc) the edge rate control (erc) circuit minimizes emi generated by the high-current switching waveform of the class-d amplifier output. one of the main contributors to emi generated by class-d amplifiers is the high- frequency energy produced by rapid (large dv/dt) transitions at the edges of the switching waveform. the erc circuit suppresses the high-frequency component of the switching waveform by extending the rise and fall times of the output fet transitions, without compromising efficiency and thd+n performance. rise and fall times are set to approximately 20ns per transition at all power levels.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 15 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression dynamic range compression (drc) the speaker amplifier?s drc can be used to limit output amplitude and reduce clipping even as the supply voltage varies. the drc allows high gain settings while preventing distortion and speaker damage. this results in louder speaker playback without increasing the maximum peak amplitude of the speaker signal path. to avoid unpredictable behavior, drc settings should not be changed while the speaker amplifier is on. figure 25 shows the speaker amplifier?s target output amplitude with respect to the drc?s input amplitude when programmed at various class-d output gain settings. the drc?s input amplitude is measured after the speaker volume control, but before the speaker amplifier block. the drc has three regions of operation: linear, compression, and limiter. when the output amplitude is initially low, the drc operates in the linear region and does not apply any gain changes to the signal. the volume control remains fixed at the level defined in sp_att. when the output amplitude has increased above the dynamic range compression threshold, the drc reduces the gain of sp_att, thereby applying compression to the output signal. the compression region is defined by the compression ratio and the dynamic range compression threshold. the dynamic range compression threshold is set by the dplt register. the dynamic range compression threshold is set 8db below the dplt threshold level. the drc applies a 2:1 compression ratio for output signals between the dynamic range compression threshold and limiter threshold. in the compression region; for every 2db rise of input amplitude, the target output amplitude only rises by 1db. this continues until the output amplitude has increased above the drc limiter threshold. the limiter region is defined by the dalc and dplt registers. in the limiter region, the target output amplitude does not increase with the input amplitude. the dplt register sets an output voltage limit independent of the battery vo ltage. this is useful for speaker protection. the da lc register defines an output voltage limit that is a percentage of the battery voltage. since the battery voltage sets the maximum output amplitude, the dalc register is used as a distortion limiter by setting the allowed clipping amount. the drc limiter threshold is defined as the lower of the two limiter voltages set by the dplt and dalc settings. for example, in figure 27; if dplt=111, dalc=001, and sv dd =4.5v pk , the drc limit is 3.79v pk as defined by dplt. however, if sv dd falls to 3.0v, the drc limiter threshold falls to 2.7v pk , as defined by dalc. the speed at which gain is c hanged is regulated by the attack and release settings in the datrt register. figure 28 shows drc attack and release behavior. drc attack occurs when the drc determines that, for given input amplitude, the actual output amplitude is higher than the target output amplitude and attack speed (defined in the datr t register) is not to be exceeded. when these criteria are met, volume is reduced by one step. drc release occurs when the drc determines that, for a given input amplitude, the ac tual output amplitude is lower than the target output amplitude and release speed (defined in the da trt register) is not be exceeded. when these criteria are met, volume is increased by one step. when the volume is changed by the drc, the sp_att register readback value remains unchanged. an internal register keeps track of the actual volume setting. when 2:1 compression is enabled, the overall gain of the speaker amplifier path is increased by 6db, as shown in figure 26. figure 25. dynamic range compression response vs. class-d output gain settings figure 26. gain boost when enabling drc \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 5 10 15 \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 50 51015 output ? level ? (dbv pk ) input ? level ? (dbv pk ) drc ?? compressor ? threshold drc ?? limiter ? threshold ? (dplt ? limiter = ?? 3.79v pk ? and ? dalc ? limiter ? off) 8db 11.57 3.57 limiter ? region compression ? region linear ? region \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 5 10 15 \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 50 51015 output ? level ? (dbv pk ) input ? level ? (dbv pk ) drc ?? compressor ? threshold 6db 3.57 12.46 v svdd = ? 4.2v ? clip threshold ? (dplt ? limiter ? off, ? dalc ? limiter ? off) compression ? region linear ? region
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 16 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression 2 2.5 3 3.5 4 4.5 5 2.533.544.555.5 agc limit (v pk ) svdd (v) dplt agc limit svdd = ? 3.0v svdd = ? 4.5v figure 27. drc limiter threshold when dplt=3.79v pk (111) and dalc=0.9*svdd (001) figure 28. drc flowchart has ? enough time ? (decay ? speed) passed ? since ? the ? last gain ? change? is ? the actual ? output amplitude ? above the ? target ? output amplitude? has ? enough time ? (attack ? speed) passed ? since ? the ? last gain ? change? reset ? the ? timers. start increase ? gain ? by 1 ? step. yes yes yes reduce ? gain ? by 1 ? step no no no does ? the ? actual output ? amplitude ? match the ? target ? output amplitude? yes no
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 17 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression speaker amplifier noise gate the speaker noise gate automatically mutes the speaker amplifier when its in put amplitude is below a predetermined noise gate threshold to reduce noise during inactivity. (this function is more useful for speech than music.) the amplitude is measured after the speaker volume control, but before the speaker amplifier block. the speaker noise gate?s threshold level is set by the sp_ng_rat register. the amplitude must be less than the noise gate threshold for the hold time determined by the ng_atrt register. the speed at which the volume is reduced is determined by the attack time setting in the ng_atrt register. when the volume is reduced by the noise gate, the sp_att register?s readback value remains unchanged. an internal register keeps track of the actual volume setting. if the speaker channel?s amplitude goes above the speaker noise gate threshold, the speaker volume is raised back to the sp_att value at a rate determined by the release time setting in the ng_atrt register. to avoid unpredictable behavior, noise gate settings should not be changed while the speaker amplifier is on. table 2. speaker volume change behavior sp_svoff sp_zcsoff behavior when sp_att is changed 1 1 volume changes immediately. 1 0 wait until a zero crossing occurs in the input before changing volume. if a zero crossing does not occur within 200s, volume is forced to the new setting. 0 1 volume is ramped to the new se tting at a rate of 200s per step. 0 0 volume is changed by one step when a zero crossing occurs. if a zero crossing does not occur within 200s, a step is forc ed. only the first zero crossing within 200s triggers a volume change; volume does not change again until the next 200s. speaker volume ramp and zero-crossing detection the sp_svoff and sp_zcsoff i 2 c bits control the speaker volume when sp_att is changed. sp_svoff and sp_zcsoff do not slow down turn-on or turn-off when using the sp_amix, sp_bmix, or srst bits. thermal, over-current, and dc offset shutdown conditions are not slowed by sp_svoff and sp_zcsoff. sp_svoff and sp_zcsoff have no effect on drc and noise gate timing. drc and noise gate timing have no effect on speaker volume ramp and zero-crossing detection. in the event of a conflict between these systems, the lowest volume setting is chosen. i 2 c control writing to and reading from registers is accomplished via the i 2 c interface. the i 2 c protocol requires that one device on the bus initiates and controls all read and write operations. this device is called the ?master? device. the master device generates the scl signal, which is the clock signal for all other devices on the bus. all other devices on the bus are called ?slave? devices. the fab2210 is a slave device. both the master and slave devices can send and receive data on the bus. during i 2 c operations, one data bit is transmitted per clock cycle. all i 2 c operations follow a repeating nine clock-cycle pattern that consis ts of eight bits (one byte) of transmitted data followed by an acknowledge (ack) or not acknowledge (nack) from the receiving device. note that there are no unused clock cycles during any operation; therefore, ther e must be no breaks in the stream of data and acks/nacks during data transfers. for most operations, i 2 c protocol requires the sda line to remain stable (unmoving) whenever scl is high; i.e. transitions on the sda line can only occur when scl is low. the exceptions to this rule are when the master device issues a start or stop condition. the slave device cannot issue a start or stop condition. start condition: this condition occurs when the sda line transitions from high to low while scl is high. the master device uses this c ondition to indicate that a data transfer is about to begin. stop condition: this condition occurs when the sda line transitions from low to high while scl is high. the master device uses this condition to signal the end of a data transfer. acknowledge and not acknowledge: when data is transferred to the slave device, the slave device sends an acknowledge (ack) after receiving every byte of data. the receiving device sends an ack by pulling sda low for one clock cycle. when the master device is reading data from the slave device, the master sends an ack after receiving every byte of data. following the last byte, a master device sends a ?not acknowledge? (nack) instead of an ack, followed by a stop condition. a nack is indicated by leaving sda high during the clock after the last byte.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 18 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression slave address each slave device on the bus must have a unique address so the master can identify which device is sending or receiving data. the fab2210 slave address is 1001101x binary where ?x? is the read/write bit. master write operations are indicated when x=0. master read operations are indicated when x=1. writing to and reading from the fab2210 all read and write operations must begin with a start condition generated by the master. after the start condition, the master must immediately send a slave address (7 bits), followed by a read/write bit. if the slave address matches the address of the fab2210, the fab2210 sends an ack after receiving the read/write bit by pulling the sda line low for one clock cycle. setting the pointer for all operations, the pointer stored in the command register must be pointing to the register that is going to be written or read. to chang e the pointer value in the command register, the read/write bit following the address must be 0. this indica tes that the master writes new information into the command register. after the fab2210 sends an ack in response to receiving the address and read/write bit, the master must transmit an appropriate 8-bit pointer value, as explained in the i 2 c registers section. the fab2210 sends an ack after receiving the new pointer data. the pointer set operation is illustrated in figure 31 and figure 32. any time a pointer set is performed, it must be immediately followed by a read or write operation. the command register retains the current pointer value between operations; therefore, once a register is indicated, subsequent read o perations do not require a pointer set cycle. write operations always require the pointer be reset. reading if the pointer is already pointing to the desired register, the master can read from t hat register by setting the read/write bit (following the slave address) to 1. after sending an ack, the fab2210 begins transmitting data during the following clock cycle. the master should respond with a nack, followed by a stop condition (see figure 29) . the master can read multiple bytes by responding to the data with an ack instead of a nack and continuing to send scl pulses, as shown in figure 30. the fab2210 increments the pointer by one and sends the data from the next register. the master indicates the last data byte by responding with a nack, followed by a stop. to read from a register other than the one currently indicated by the command register, a pointer to the desired register must be set. immediately following the pointer set, the master must perform a repeat start condition (see figure 32) , which indicates to the fab2210 that a new operation is about to occur. if the repeat start condition does not occur, the fab2210 assumes that a write is taking place and the selected register is overwritten by the upcoming data on the data bus. after the star t condition, the master must again send the device address and read/write bit. this time, the read/write bit must be set to 1 to indicate a read. the rest of the read cycle is the same as described in the previous paragraphs for reading from a preset pointer location. writing all writes must be preceded by a pointer set, even if the pointer is already pointing to the desired register. immediately following the po inter set, the master must begin transmitting the data to be written. after transmitting each byte of data, the master must release the serial data (sda) line for one clock cycle to allow the fab2210 to acknowledge receiving the byte. the write operation should be terminated by a stop condition from the master (see figure 31) . as with reading, the master can write multiple bytes by continuing to send data. the fab2210 increments the pointer by one and accepts data for the next register. the master indicates the last data byte by issuing a stop condition.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 19 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression read / write diagrams figure 29. i 2 c read figure 30. i 2 c multiple byte read figure 31. i 2 c write figure 32. i 2 c write followed by read
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 20 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression register map the i 2 c slave address is 1001101x, where x=0 for write operations and x=1 for read operations. addr b7 b6 b5 b4 b3 b2 b1 b0 0x15 revision_id[2:0] rsvd rsvd dcerr_time[1:0] 0 0x1a 0 softvol rsvd 0x1b 0 drcmin[6:0] 0x1d mcssmt[2:0] ssmt[2:0] erc 0 0x80 srst 0 0 0 0 1 0 0 0x81 drc_mode[1:0] datrt[1:0] ng_atrt[1:0] 0 modesel 0x82 dplt[2:0] hp_ng_rat[2:0] hp_ng_att[1:0] 0x83 0 0 nclip sp_ng_rat[2:0] sp_ng_att[1:0] 0x84 va[3:0] vb[3:0] 0x85 difa difb 0 0 hp_svoff hp_hiz sp_svoff sp_hiz 0x86 0 sp_att[6:0] 0x87 0 hp_att[6:0] 0x88 ocp_err otp_err dc_err hp_mono hp_amix hp_bmix sp_amix sp_bmix 0xc0 0 dalc[2:0] hp_gain[1:0] sp_gain[1:0] 0xc1 0 0 0 0 0 hp_zcsoff 0 sp_zcsoff notes: 6. bits labeled ?0? are reserved. only zeros should be written to these bits. 7. bits labeled ?1? are reserved. only ones should be written to these bits. 8. bits labeled ?rsvd? are for testing only. writing to these bits has no effect. when read, they may return any value. 9. bits and addresses not listed in the register map are for testing only. these bits should never be written. when read, they may return any value. register descriptions ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? addr b7 b6 b5 b4 b3 b2 b1 b0 0x15 revision_id[2:0] rsvd rsvd dcerr_time[1:0] 0 default 0 1 1 0 0 0 revision_id[2:0] (read only) 011 = silicon revision 3. dcerr_time[1:0] dc error time control 11=dc output detection disabled 10=15ms 01=5ms 00=2ms addr b7 b6 b5 b4 b3 b2 b1 b0 0x1a 0 softvol rsvd default 0 0
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 21 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression softvol sets volume ramp speed; sets noise gate release speed when modesel=1. 1=2ms/step 0=200s/step addr b7 b6 b5 b4 b3 b2 b1 b0 0x1b 0 drcmin[6:0] default 0 0 0 0 0 0 0 0 drcmin[6:0] sets the minimum gain that the drc applies to a signal during attack. drcmin [6:0] speaker volume (db) drcmin [6:0] speaker volume (db) drcmin [6:0] speaker volume (db) drcmin [6:0] speaker volume (db) 1111111 0.00 1011111 -10.00 0111111 -36.00 0011111 reserved 1111110 -0.25 1011110 -10.50 0111110 -37.00 0011110 reserved 1111101 -0.50 1011101 -11.00 0111101 -38.00 0011101 reserved 1111100 -0.75 1011100 -11.50 0111100 -39.00 0011100 reserved 1111011 -1.00 1011011 -12.00 0111011 -40.00 0011011 reserved 1111010 -1.25 1011010 -12.50 0111010 -41.00 0011010 reserved 1111001 -1.50 1011001 -13.00 0111001 -42.00 0011001 reserved 1111000 -1.75 1011000 -13.50 0111000 -43.00 0011000 reserved 1110111 -2.00 1010111 -14.00 0110111 -44.00 0010111 reserved 1110110 -2.25 1010110 -14.50 0110110 -45.00 0010110 reserved 1110101 -2.50 1010101 -15.00 0110101 -46.00 0010101 reserved 1110100 -2.75 1010100 -15.50 0110100 -47.00 0010100 reserved 1110011 -3.00 1010011 -16.00 0110011 -48.00 0010011 reserved 1110010 -3.25 1010010 -17.00 0110010 -49.00 0010010 reserved 1110001 -3.50 1010001 -18.00 0110001 -50.00 0010001 reserved 1110000 -3.75 1010000 -19.00 0110000 -51.00 0010000 reserved 1101111 -4.00 1001111 -20.00 0101111 -52.00 0001111 reserved 1101110 -4.25 1001110 -21.00 0101110 -53.00 0001110 reserved 1101101 -4.50 1001101 -22.00 0101101 -54.00 0001101 reserved 1101100 -4.75 1001100 -23.00 0101100 -55.00 0001100 reserved 1101011 -5.00 1001011 -24.00 0101011 -56.00 0001011 reserved 1101010 -5.25 1001010 -25.00 0101010 -57.00 0001010 reserved 1101001 -5.50 1001001 -26.00 0101001 -58.00 0001001 reserved 1101000 -5.75 1001000 -27.00 0101000 -59.00 0001000 reserved 1100111 -6.00 1000111 -28.00 0100111 -60.00 0000111 reserved 1100110 -6.50 1000110 -29.00 0100110 -61.00 0000110 reserved 1100101 -7.00 1000101 -30.00 0100101 -62.00 0000101 reserved 1100100 -7.50 1000100 -31.00 0100100 -63.00 0000100 reserved 1100011 -8.00 1000011 -32.00 0100011 -64.00 0000011 reserved 1100010 -8.50 1000010 -33.00 0100010 reserved 0000010 reserved 1100001 -9.00 1000001 -34.00 0100001 reserved 0000001 reserved 1100000 -9.50 1000000 -35.00 0100000 reserved 0000000 mute
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 22 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression addr b7 b6 b5 b4 b3 b2 b1 b0 0x1d mcssmt[2:0] ssmt[2:0] erc 0 default 1 0 0 0 0 0 1 0 mcssmt[2:0] sets the master clock spread spectrum modulation perc entage. a setting of 000 results in a 9.4% modulation. modulating the master clock does not modulate the class- d output frequency because the triangle wave generator is pll controlled. mcssmt[2:0] modulation % 111 10.3 110 9.0 101 8.5 100 6.5 011 37.7 010 21.6 001 15.6 000 9.4 ssmt[2:0] sets the class-d spread-spectrum modulation percentag e. a setting of 000 results in 9.4% modulation. ssmt[2:0] modulation % 111 10.3 110 9.0 101 8.5 100 6.5 011 37.7 010 21.6 001 15.6 000 9.4 erc 1=class-d edge rate control on. 0=class-d edge rate control off. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? addr b7 b6 b5 b4 b3 b2 b1 b0 0x80 srst 0 0 0 0 1 0 0 default 1 0 0 0 0 1 0 0
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 23 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression srst 1=low-power standby mode. all registers ar e reset to their default values. all i 2 c write commands to bits other than srst are ignored. 0=normal operation. addr b7 b6 b5 b4 b3 b2 b1 b0 0x81 drc_mode[1:0] datrt[1:0] ng_atrt[1:0] 0 modesel default 0 0 0 1 1 1 0 0 drc_mode[1:0] sets the drc?s compression ratio. drc_mode[1:0] compression ratio 11 reserved 10 reserved 01 2:1 00 off datrt[1:0] sets the drc?s attack and release times. to avoid extraneo us noise, do not change this setting while the speaker amplifier is on. datrt[1:0] attack time (ms/step) release time (ms/step) 11 1.0 200 10 0.5 200 01 0.1 200 00 0.1 20 ng_atrt[1:0], modesel sets the noise gate attack, hold, and release times for the headphone and speaker amplifiers. to avoid extraneous noise, do not change this setting while the headphone or speaker amplifiers are on. modesel ng_atrt[1:0] attack time (ms/step) release time (s/step) softvol=0 release time (s/step) softvol=1 hold time (ms) 1 11 800 200 2000 44 1 10 400 200 2000 44 1 01 100 200 2000 44 1 00 25 200 2000 44 0 11 800 1400 1400 44 0 10 400 1400 1400 44 0 01 100 1400 1400 44 0 00 25 1400 1400 44 addr b7 b6 b5 b4 b3 b2 b1 b0 0x82 dplt[2:0] hp_ng_rat[2:0] hp_ng_att[1:0] default 0 0 0 1 0 0 0 0
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 24 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression dplt[2:0] sets the drc?s limiter value, regardless of svdd supply voltage. also sets dynamic range compression threshold. to avoid extraneous noise, do not change th is setting while the speaker amplifier is on. dplt[2:0] limiter voltage (v pk ) maximum power with sine wave and 8 ? load (mw) drc threshold at class-d output (db v pk ) 111 3.79 900 -12.5 110 3.69 850 -12.7 101 3.58 800 -13.0 100 3.46 750 -13.3 011 3.35 700 -13.5 010 3.22 650 -13.8 001 3.10 600 -14.0 000 no limit no limit -12.5 hp_ng_rat[2:0] sets the headphone noise gate threshold level. detectio n is at the input to the headphone volume block. hp_ng_rat[2:0] threshold (mv pk ) 111 reserved 110 reserved 101 18 100 12 011 noise gate disabled 010 noise gate disabled 001 noise gate disabled 000 noise gate disabled hp_ng_att[1:0] sets the headphone noise gate attenuation level. hp_ng_att[1:0] attenuation level (db) 11 -6.0 10 -12.0 01 -18.0 00 mute addr b7 b6 b5 b4 b3 b2 b1 b0 0x83 0 0 nclip sp_ng_rat[2:0] sp_ng_att[1:0] default 0 0 0 1 0 0 0 0 nclip 1=turns on the drc?s clip limiter. amount of clipping is set by dalc. 0=drc clip limiter is disabled.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 25 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression sp_ng_rat [2:0] sets the speaker noise gate threshold. de tection is at the output of the speaker volume block. to avoid extraneous noise, do not change this setting while the speaker amplifier is on. sp_ng_rat[2:0] threshold (mv pk ) 111 reserved 110 reserved 101 29 100 24 011 14 010 9 001 6 000 noise gate disabled sp_ng_att[1:0] sets the speaker noise gate attenuation level. sp_ng_att[1:0] attenuation level (db) 11 mute 10 -10 01 -20 00 -40 addr b7 b6 b5 b4 b3 b2 b1 b0 0x84 va[3:0] vb[3:0] default 0 0 1 0 0 0 1 0 va[3:0], vb[3:0] sets pre-amplifier gain. va[3:0] or vb[3:0] gain (db) va[3:0] or vb[3:0] gain (db) 1111 reserved 0111 7.5 1110 reserved 0110 6.0 1101 reserved 0101 4.5 1100 18.0 0100 3.0 1011 15.0 0011 1.5 1010 12.0 0010 0.0 1001 10.5 0001 -1.5 1000 9.0 0000 -3.0
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 26 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression addr b7 b6 b5 b4 b3 b2 b1 b0 0x85 difa difb 0 0 hp_svoff hp_hiz sp_svoff sp_hiz default 0 0 0 0 0 1 0 0 difa 1=ina1 and ina2 are configured as a differential pair. 0=ina1 and ina2 are configured as separate single-ended inputs. difb 1=inb1 and inb2 are configured as a differential pair. 0=inb1 and inb2 are configured as separate single-ended inputs. hp_svoff 1=headphone volume ramping is off. 0=headphone volume ramping is on. hp_hiz 1=headphone amplifier output impedance is 12.5k ? when amplifier is off and srst=0. 0=headphone amplifier output is shorted to dgnd when amplifier is off and srst=0. sp_svoff 1=speaker volume ramping is off. 0=speaker volume ramping is on. sp_hiz 1=speaker amplifier output is high impe dance when amplifier is off and srst=0. 0=speaker amplifier output is conn ected to sgnd with an internal 2k ? resistor when amplifier is off and srst=0.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 27 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression addr b7 b6 b5 b4 b3 b2 b1 b0 0x86 0 sp_att[6:0] default 0 0 0 0 0 0 0 0 sp_att[6:0] sets the speaker volume. sp_att [6:0] speaker volume (db) sp_att [6:0] speaker volume (db) sp_att [6:0] speaker volume (db) sp_att [6:0] speaker volume (db) 1111111 0.00 1011111 -10.00 0111111 -36.00 0011111 reserved 1111110 -0.25 1011110 -10.50 0111110 -37.00 0011110 reserved 1111101 -0.50 1011101 -11.00 0111101 -38.00 0011101 reserved 1111100 -0.75 1011100 -11.50 0111100 -39.00 0011100 reserved 1111011 -1.00 1011011 -12.00 0111011 -40.00 0011011 reserved 1111010 -1.25 1011010 -12.50 0111010 -41.00 0011010 reserved 1111001 -1.50 1011001 -13.00 0111001 -42.00 0011001 reserved 1111000 -1.75 1011000 -13.50 0111000 -43.00 0011000 reserved 1110111 -2.00 1010111 -14.00 0110111 -44.00 0010111 reserved 1110110 -2.25 1010110 -14.50 0110110 -45.00 0010110 reserved 1110101 -2.50 1010101 -15.00 0110101 -46.00 0010101 reserved 1110100 -2.75 1010100 -15.50 0110100 -47.00 0010100 reserved 1110011 -3.00 1010011 -16.00 0110011 -48.00 0010011 reserved 1110010 -3.25 1010010 -17.00 0110010 -49.00 0010010 reserved 1110001 -3.50 1010001 -18.00 0110001 -50.00 0010001 reserved 1110000 -3.75 1010000 -19.00 0110000 -51.00 0010000 reserved 1101111 -4.00 1001111 -20.00 0101111 -52.00 0001111 reserved 1101110 -4.25 1001110 -21.00 0101110 -53.00 0001110 reserved 1101101 -4.50 1001101 -22.00 0101101 -54.00 0001101 reserved 1101100 -4.75 1001100 -23.00 0101100 -55.00 0001100 reserved 1101011 -5.00 1001011 -24.00 0101011 -56.00 0001011 reserved 1101010 -5.25 1001010 -25.00 0101010 -57.00 0001010 reserved 1101001 -5.50 1001001 -26.00 0101001 -58.00 0001001 reserved 1101000 -5.75 1001000 -27.00 0101000 -59.00 0001000 reserved 1100111 -6.00 1000111 -28.00 0100111 -60.00 0000111 reserved 1100110 -6.50 1000110 -29.00 0100110 -61.00 0000110 reserved 1100101 -7.00 1000101 -30.00 0100101 -62.00 0000101 reserved 1100100 -7.50 1000100 -31.00 0100100 -63.00 0000100 reserved 1100011 -8.00 1000011 -32.00 0100011 -64.00 0000011 reserved 1100010 -8.50 1000010 -33.00 0100010 reserved 0000010 reserved 1100001 -9.00 1000001 -34.00 0100001 reserved 0000001 reserved 1100000 -9.50 1000000 -35.00 0100000 reserved 0000000 mute
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 28 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression addr b7 b6 b5 b4 b3 b2 b1 b0 0x87 0 hp_att[6:0] default 0 0 0 0 0 0 0 0 hp_att[6:0] sets the headphone volume. hp_att [6:0] headphone volume (db) hp_att [6:0] headphone volume (db) hp_att [6:0] headphone volume (db) hp_att [6:0] headphone volume (db) 1111111 0.00 1011111 -10.00 0111111 -36.00 0011111 reserved 1111110 -0.25 1011110 -10.50 0111110 -37.00 0011110 reserved 1111101 -0.50 1011101 -11.00 0111101 -38.00 0011101 reserved 1111100 -0.75 1011100 -11.50 0111100 -39.00 0011100 reserved 1111011 -1.00 1011011 -12.00 0111011 -40.00 0011011 reserved 1111010 -1.25 1011010 -12.50 0111010 -41.00 0011010 reserved 1111001 -1.50 1011001 -13.00 0111001 -42.00 0011001 reserved 1111000 -1.75 1011000 -13.50 0111000 -43.00 0011000 reserved 1110111 -2.00 1010111 -14.00 0110111 -44.00 0010111 reserved 1110110 -2.25 1010110 -14.50 0110110 -45.00 0010110 reserved 1110101 -2.50 1010101 -15.00 0110101 -46.00 0010101 reserved 1110100 -2.75 1010100 -15.50 0110100 -47.00 0010100 reserved 1110011 -3.00 1010011 -16.00 0110011 -48.00 0010011 reserved 1110010 -3.25 1010010 -17.00 0110010 -49.00 0010010 reserved 1110001 -3.50 1010001 -18.00 0110001 -50.00 0010001 reserved 1110000 -3.75 1010000 -19.00 0110000 -51.00 0010000 reserved 1101111 -4.00 1001111 -20.00 0101111 -52.00 0001111 reserved 1101110 -4.25 1001110 -21.00 0101110 -53.00 0001110 reserved 1101101 -4.50 1001101 -22.00 0101101 -54.00 0001101 reserved 1101100 -4.75 1001100 -23.00 0101100 -55.00 0001100 reserved 1101011 -5.00 1001011 -24.00 0101011 -56.00 0001011 reserved 1101010 -5.25 1001010 -25.00 0101010 -57.00 0001010 reserved 1101001 -5.50 1001001 -26.00 0101001 -58.00 0001001 reserved 1101000 -5.75 1001000 -27.00 0101000 -59.00 0001000 reserved 1100111 -6.00 1000111 -28.00 0100111 -60.00 0000111 reserved 1100110 -6.50 1000110 -29.00 0100110 -61.00 0000110 reserved 1100101 -7.00 1000101 -30.00 0100101 -62.00 0000101 reserved 1100100 -7.50 1000100 -31.00 0100100 -63.00 0000100 reserved 1100011 -8.00 1000011 -32.00 0100011 -64.00 0000011 reserved 1100010 -8.50 1000010 -33.00 0100010 reserved 0000010 reserved 1100001 -9.00 1000001 -34.00 0100001 reserved 0000001 reserved 1100000 -9.50 1000000 -35.00 0100000 reserved 0000000 mute
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 29 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression addr b7 b6 b5 b4 b3 b2 b1 b0 0x88 ocp_err otp_err dc_err hp_mono hp_amix hp_bmix sp_amix sp_bmix default 0 0 0 0 0 ocp_err (read only) 1=indicates that the speaker am plifier current limit of 1.3a peak has been exceeded. speaker amplifier turns off. bit remains high and amplifier stays off until power or srst are cycled. 0=normal operation. otp_err (read only) 1=indicates that the temperat ure limit of 150c has been exceeded. speaker am plifier turns off. bit remains high and amplifier stays off until temperature falls below thermal shutdown hysteresis (see electrical characteristics) or power or srst are cycled. 0=normal operation. dc_err (read only) 1=indicates that the dc voltage across the s peaker amplifier terminals has exceeded 1.5v pk . speaker amplifier turns off. bit remains high and amplifier stays off until power or srst are cycled. 0=normal operation.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 30 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression hp_mono, hp_amix, hp_bmix selects inputs to the headphone amplifiers. hp_mono difa difb hp_amix hp_bmix houtl houtr 1 1 1 1 1 (ina1-ina2+inb1-inb2)/2 amplifier off 1 1 1 1 0 (ina1-ina2)/2 amplifier off 1 1 1 0 1 (inb1-inb2)/2 amplifier off 1 1 1 0 0 amplifier off amplifier off 1 1 0 1 1 (ina1-ina2+inb1+inb2)/2 amplifier off 1 1 0 1 0 (ina1-ina2)/2 amplifier off 1 1 0 0 1 (inb1+inb2)/2 amplifier off 1 1 0 0 0 amplifier off amplifier off 1 0 1 1 1 (ina1+ina2+inb1-inb2)/2 amplifier off 1 0 1 1 0 (ina1+ina2)/2 amplifier off 1 0 1 0 1 (inb1-inb2)/2 amplifier off 1 0 1 0 0 amplifier off amplifier off 1 0 0 1 1 (ina1+ina2+inb1+inb2)/2 amplifier off 1 0 0 1 0 (ina1+ina2)/2 amplifier off 1 0 0 0 1 (inb1+inb2)/2 amplifier off 1 0 0 0 0 amplifier off amplifier off 0 1 1 1 1 (ina1-ina2+inb1-inb2) (ina1-ina2+inb1-inb2) 0 1 1 1 0 (ina1-ina2) (ina1-ina2) 0 1 1 0 1 (inb1-inb2) (inb1-inb2) 0 1 1 0 0 amplifier off amplifier off 0 1 0 1 1 [(ina1-ina2)]+inb1 [(ina1-ina2)]+inb2 0 1 0 1 0 (ina1-ina2) (ina1-ina2) 0 1 0 0 1 inb1 inb2 0 1 0 0 0 amplifier off amplifier off 0 0 1 1 1 ina1+[(inb1-inb2)] ina2+[(inb1-inb2)] 0 0 1 1 0 ina1 ina2 0 0 1 0 1 (inb1-inb2) (inb1-inb2) 0 0 1 0 0 amplifier off amplifier off 0 0 0 1 1 ina1+ inb1 ina2+inb2 0 0 0 1 0 ina1 ina2 0 0 0 0 1 inb1 inb2 0 0 0 0 0 amplifier off amplifier off
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 31 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression sp_amix, sp_bmix selects inputs to the speaker amplifier. difa difb sp_amix sp_bmix speaker volume inputs 1 1 1 1 (ina1-ina2+inb1-inb2)/2 1 1 1 0 (ina1-ina2)/2 1 1 0 1 (inb1-inb2)/2 1 1 0 0 speaker amplifier off 1 0 1 1 (ina1-ina2+inb1+inb2)/2 1 0 1 0 (ina1-ina2)/2 1 0 0 1 (inb1+inb2)/2 1 0 0 0 speaker amplifier off 0 1 1 1 (ina1+ina2+inb1-inb2)/2 0 1 1 0 (ina1+ina2)/2 0 1 0 1 (inb1-inb2)/2 0 1 0 0 speaker amplifier off 0 0 1 1 (ina1+ina2+inb1+inb2)/2 0 0 1 0 (ina1+ina2)/2 0 0 0 1 (inb1+inb2)/2 0 0 0 0 speaker amplifier off addr b7 b6 b5 b4 b3 b2 b1 b0 0xc0 0 dalc[2:0] hp_gain[1:0] sp_gain[1:0] default 0 0 0 1 0 0 0 0 dalc[2:0] sets the drc?s clip limiter. to avoid extraneous noise, do not change this setting while the speaker amplifier is on. dalc[2:0] svdd fraction (v/v) thd with 1khz sine wave (%) (v svdd =3.7v, 8 ? load) 111 reserved reserved 110 reserved reserved 101 reserved reserved 100 1.15 10 011 1.00 4.9 010 0.95 3 001 0.90 1 000 reserved reserved
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 32 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression hp_gain[1:0] sets the gain of the headphone amplifier block. hp_gain[1:0] headphone amplifier gain (db) 11 6.0 10 3.0 01 1.5 00 0 sp_gain[1:0] sets the speaker amplifier gain. sp_gain[1:0] speaker amplifier gain (db) 11 reserved 10 24 01 20 00 16 addr b7 b6 b5 b4 b3 b2 b1 b0 0xc1 0 0 0 0 0 hp_zcsoff 0 sp_zcsoff default 0 0 0 0 0 1 0 1 sp_zcsoff 1=speaker volume zero-crossing detection is off. 0=speaker volume zero-crossing detection is on. hp_zcsoff 1=headphone volume zero-c rossing detection is off. 0=headphone volume zero-crossing detection is on.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 33 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression applications information layout considerations general layout and supply bypassing play a major role in analog performance and thermal characteristics. fairchild provides a demonstration board to guide layout and aid device evaluation. a graphical user interface software program allows control of the i 2 c registers to optimize the performance of the device in various applications. for the best results, follow the steps and recommended routing rules listed below. recommended routing/layout rules ? do not run analog and digital signals in parallel. ? use separate analog and digital power planes to supply power. ? traces should run on top of the ground plane at all times. ? no trace should run over ground/power splits. ? avoid routing at 90-degree angles. ? place bypass capacitors within 2.54mm (0.1 inches) of the device power pin. ? minimize all trace lengths to reduce series inductance.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 34 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression physical dimensions external product dimensions product d e x y FAB2210UCX 1.96mm 1.96mm 0.018mm 0.018mm package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ve rify or obtain the most recent version. pa ckage specifications do not expand fairchild?s worldwide terms and conditions, specifical ly the warranty therein, which covers fairchild products. always visit fairchild semiconductors on line packaging area for the most recent packaging drawings and tape and reel specifications: http://www.fairchildsemi.com/packaging/ . bottom view side views top view ball a1 index area 1 2 3 4 a b c d e seating plane 20x a1 c 0.005 cab f ?0.2600.02 e d b a 0.625 0.547 0.06 c 0.05 c e d f 0.3780.018 0.2080.021 notes: a. no jedec registration applies. b. dimensions are in millimeters. c. dimensions and tolerance per asmey14.5m, 1994. d. datum c is defined by the spherical crowns of the balls. e. package nominal height is 586 microns 39 microns (547-625 microns). f. for dimensions d, e, x, and y see product datasheet. g. drawing filname: mkt-uc020aarev2. 0.03 c 2x 0.03 c 2x 0.40 1.20 0.40 1.60 (y) 0.018 (x) 0.018 recommended land pattern (nsmd type) ?0.20 cu pad ?0.30 solder mask opening 0.40 1.20 0.40 1.60
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fab2210 ? rev. 1.1.1 35 fab2210 ? audio subsystem with class-g headphone and 3.3w mono class-d speaker with dynamic range compression

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